Not Applicable
Not Applicable
The present invention relates to semiconductor integrated circuits. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and dynamic random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.
Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of memories, including non-volatile and volatile memories. The volatile memory, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its stored data if the power applied has been turned off. SRAMs and DRAMs often include a multitude of memory cells disposed in a two dimensional array. Due to its larger memory cell size, an SRAM is typically more expensive to manufacture than a DRAM. An SRAM typically, however, has a smaller read access time and a lower power consumption than a DRAM. Therefore, where fast access to data or low power is needed, SRAMs are often used to store the data.
Non-volatile semiconductor memory devices are also well known. A non-volatile semiconductor memory device, such as flash Erasable Programmable Read Only Memory (Flash EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) or, Metal Nitride Oxide Semiconductor (MNOS), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data.
Unfortunately, the non-volatile semiconductor memory is typically slower to operate than a volatile memory. Therefore, where fast store and retrieval of data is required, the non-volatile memory is not typically used. Furthermore, the non-volatile memory often requires a high voltage, e.g., 12 volts, to program or erase. Such high voltages may cause a number of disadvantages. The high voltage increases the power consumption and thus shortens the lifetime of the battery powering the memory. The high voltage may degrade the ability of the memory to retain its charges due to hot-electron injection. The high voltage may cause the memory cells to be over-erased during erase cycles. Cell over-erase results in faulty readout of data stored in the memory cells.
The growth in demand for battery-operated portable electronic devices, such as cellular phones or personal organizers, has brought to the fore the need to dispose both volatile as well as non-volatile memories within the same portable device. When disposed in the same electronic device, the volatile memory is typically loaded with data during a configuration cycle. The volatile memory thus provides fast access to the stored data. To prevent loss of data in the event of a power failure, data stored in the volatile memory is often also loaded into the non-volatile memory either during the configuration cycle, or while the power failure is in progress. After power is restored, data stored in the non-volatile memory is read and stored in the non-volatile memory for future access. Unfortunately, most of the portable electronic devices may still require at least two devices, including the non-volatile and volatile, to carry out backup operations. Two devices are often required since each of the devices often rely on different process technologies, which are often incompatible with each other.
To increase the battery life and reduce the cost associated with disposing both non-volatile and volatile memory devices in the same electronic device, non-volatile SRAMs and non-volatile DRAMs have been developed. Such devices have the non-volatile characteristics of non-volatile memories, i.e., retain their charge during a power-off cycle, but provide the relatively fast access times of the volatile memories.
As merely an example, FIG. 1 is a transistor schematic diagram of a prior art non-volatile DRAM 10. Non-volatile DRAM 10 includes transistors 12, 14, 16 and EEPROM cell 18. The control gate and the drain of EEPROM cell 18 form the DRAM capacitor. Transistors 12 and 14 are parts of the DRAM cell. Transistor 16 is the mode selection transistor and thus selects between the EEPROM and the DRAM mode. EEPROM cell 18 may suffer from the high voltage problems, is relatively large and thus is expensive.
Accordingly, a need continues to exist for a relatively small non-volatile DRAM that consumes less power than those in the prior art, does not suffer from read errors caused by over-erase, and is not degraded due to hot-electron injection.
While the invention is described in conjunction with the preferred embodiments, this description is not intended in any way as a limitation to the scope of the invention. Modifications, changes, and variations, which are apparent to those skilled in the art can be made in the arrangement, operation and details of construction of the invention disclosed herein without departing from the spirit and scope of the invention.
According to the present invention, an improved memory device and method is provided. More particularly, the invention provides a semiconductor memory that has integrated non-volatile and dynamic random access memory cells. Although the invention has been applied to a single integrated circuit device in a memory application, there can be other alternatives, variations, and modifications. For example, the invention can be applied to embedded memory applications, including those with logic or micro circuits, and the like.
In accordance with the present invention, a memory cell includes a non-volatile device and a dynamic random access memory (DRAM) cell. The DRAM cell includes an MOS transistor having a drain terminal coupled to a bitline associated with the memory cell, a gate terminal coupled to a first terminal of the memory cell, and a source terminal coupled a first node of the memory cell having an associated capacitance. The non-volatile device is adapted to receive from or supply charges to the DRAM cell. The non-volatile device includes a substrate region coupled to a second terminal of the memory, a source region formed in the substrate region and coupled to the first node, a drain region formed in the substrate region and separated form the source region by a first channel region, a first gate overlaying a first portion of the channel region and separated therefrom via a first insulating layer, and a second gate overlaying a second portion of the channel region and separated therefrom via a second insulating layer. The first portion and second portions of the channel region do not overlap. The drain region of the non-volatile device is coupled to the third terminal of the memory cell. The first gate of the non-volatile device is coupled to the fourth terminal of the memory cell. The second gate of the non-volatile device is coupled to the fifth terminal of the memory cell.
The DRAM cell may be programmed during a write cycle. During such a programming cycle, the first terminal of the memory cell is raised to a high voltage to enable the voltage present on the bitline associated with the memory to be stored across the DRAM""s capacitor. Data may also be transferred to the DRAM cells from the non-volatile devices after the non-volatile devices has been programmed. To load (store) the data stored in the non-volatile devices in the DRAM cell, the third, fourth and fifth terminals of the memory cell are raised to a relatively high first voltage and the first terminal of the memory cell is raised to a second relatively high voltage.
While the power is being turned off or is abruptly interrupted or as needed, the data stored in the DRAM cell is stored in the non-volatile device. Prior to storing the data in the non-volatile devices, the non-volatile device is erased by applying a relatively high negative voltage to the third terminal of the memory cell, while applying, e.g., 0 volt to the remaining terminals of the memory cell.
To reload the data in the DRAM cells after power is restored, a relatively high voltage is applied to the third, fourth and fifth terminals of the memory cell, and another relatively high voltage is applied to the first terminal of the memory cell. A read sensing voltage is applied to the bitline associated with the memory cell. The read sensing voltage is so selected as to disable current flow in the programmed non-volatile device and/or to enable current flow in the erased non-volatile device, thereby causing the DRAM cell to be reprogrammed with data it had prior to power supply termination or failure.
The accompanying drawings, which are incorporated in and form part of the specification, illustrate embodiments of the invention and, together with the description, sever to explain the principles of the invention.